`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:10:48 03/23/2012 
// Design Name: 
// Module Name:    InternalBridge 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module InternalBridge(
  input               CLK,
  input               RST,
  
  input               S_PRI_TVALID,
  output              S_PRI_TREADY,
  input   [127:0]     S_PRI_TDATA,
  input   [3:0]       S_PRI_TSTRB,
  input               S_PRI_TLAST,
  output              M_PRI_TVALID,
  input               M_PRI_TREADY,
  output  [127:0]     M_PRI_TDATA,
  output  [3:0]       M_PRI_TSTRB,
  output              M_PRI_TLAST,
  
  input               S_SEC_TVALID,
  output              S_SEC_TREADY,
  input   [127:0]     S_SEC_TDATA,
  input   [3:0]       S_SEC_TSTRB,
  input               S_SEC_TLAST,
  output              M_SEC_TVALID,
  input               M_SEC_TREADY,
  output  [127:0]     M_SEC_TDATA,
  output  [3:0]       M_SEC_TSTRB,
  output              M_SEC_TLAST,
  
  output [31:12] io_base,
  output [31:12] io_limit,
  output [31:20] mem_base,
  output [31:20] mem_limit,
  output [63:20] pmem_base,
  output [63:20] pmem_limit,
  output [7:0]   secondary_bus,
  output [7:0]   subordinate_bus  
  );

  wire [31:0]   ppb_CfgDo;
  wire [31:0]   ppb_CfgDi;
  wire [3:0]    ppb_CfgBe;
  wire [9:0]    ppb_CfgAddr;
  wire          ppb_CfgWe;
  wire          ppb_CfgReq;
  wire          ppb_CfgAck;

  ppb 
  bridge(
    .CLK            (CLK),
    .RST            (RST),

    .s_pri_tvalid   (S_PRI_TVALID),
    .s_pri_tready   (S_PRI_TREADY),
    .s_pri_tdata    (S_PRI_TDATA ),
    .s_pri_tstrb    (S_PRI_TSTRB ),
    .s_pri_tlast    (S_PRI_TLAST ),
    .m_pri_tvalid   (M_PRI_TVALID),
    .m_pri_tready   (M_PRI_TREADY),
    .m_pri_tdata    (M_PRI_TDATA ),
    .m_pri_tstrb    (M_PRI_TSTRB ),
    .m_pri_tlast    (M_PRI_TLAST ),
  
    .s_sec_tvalid   (S_SEC_TVALID),
    .s_sec_tready   (S_SEC_TREADY),
    .s_sec_tdata    (S_SEC_TDATA ),
    .s_sec_tstrb    (S_SEC_TSTRB ),
    .s_sec_tlast    (S_SEC_TLAST ),
    .m_sec_tvalid   (M_SEC_TVALID),
    .m_sec_tready   (M_SEC_TREADY),
    .m_sec_tdata    (M_SEC_TDATA ),
    .m_sec_tstrb    (M_SEC_TSTRB ),
    .m_sec_tlast    (M_SEC_TLAST ),
    
    .CfgDo          (ppb_CfgDo  ),
    .CfgDi          (ppb_CfgDi  ),
    .CfgBe          (ppb_CfgBe  ),
    .CfgAddr        (ppb_CfgAddr),
    .CfgWe          (ppb_CfgWe  ),
    .CfgReq         (ppb_CfgReq ),
    .CfgAck         (ppb_CfgAck ),
    
    .io_base        (io_base        ),
    .io_limit       (io_limit       ),
    .mem_base       (mem_base       ),
    .mem_limit      (mem_limit      ),
    .pmem_base      (pmem_base      ),
    .pmem_limit     (pmem_limit     ),
    .primary_bus    (primary_bus    ),
    .secondary_bus  (secondary_bus  ),
    .subordinate_bus(subordinate_bus)
    );

  ConfigurationSpace #(
    .DEVICE_TYPE (4'h1),
    .HEADER_TYPE (8'h01),
    .CLASS_CODE  (24'h060400),
//    .CAPABILITIES_PTR(8'h0),
    .BAR0(32'h0),
    .BAR1(32'h0))
  cs(
    .clk            (CLK),
    .rst            (RST),

    .di         (ppb_CfgDo),
    .do         (ppb_CfgDi),
    .byte_en    (ppb_CfgBe),
    .rd_wr_done (ppb_CfgAck),
    .dwaddr     (ppb_CfgAddr),
    .rd_en      (ppb_CfgReq && !ppb_CfgWe),
    .wr_en      (ppb_CfgReq && ppb_CfgWe),
    
    .Status     (cfg_status),
    .Command    (cfg_command)
  );
endmodule
